Huawei’s Ascend 960 gets dramatically bigger as UnifiedBus links thousands of processors for increasingly massive AI model workloads | Daily Reports Online
- Huawei’s Ascend 960 roadmap depends on scale, memory, and faster interconnects
- UnifiedBus connects thousands of processors while reducing communication bottlenecks inside AI systems
- The Atlas 960 roadmap reaches 15,488 processors with 34 PB/s bandwidth
Huawei is expanding its Ascend platform with larger systems designed to handle AI models containing up to 10 trillion parameters.
The company is advancing UnifiedBus, an interconnect architecture intended to connect processors, memory, and storage with lower communication overhead.
That approach gives Huawei another way to compensate for hardware limitations that have constrained individual Ascend accelerators against Nvidia’s products.
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Huawei expands the Ascend 960 system
Huawei’s Atlas 960 SuperPoD roadmap calls for systems containing as many as 15,488 Ascend 960 processors, up from its earlier 8,192 processor configuration.
The company says the system can deliver 30 EFLOPS of FP8 computing and 60 EFLOPS using FP4, alongside 4,460 TB of memory capacity.
Its interconnect bandwidth is specified at 34 PB/s, while Huawei expects training performance to reach 15.9 million tokens per second.
Huawei has also accelerated development of the Ascend 960 family, with the 960DT scheduled for Q1 2027 and the 960PR planned for Q3 2027.
The company says both versions will arrive earlier than previously expected, while Huawei says performance improvements have exceeded the original roadmap.
“We’re evolving our Ascend chip series on a one-generation-a-year cycle,” said David Wang, deputy chairman and rotating chairman of Huawei.
“In 2028 and 2029, we will roll out the Ascend 970 and 980 chips, respectively. Thanks to the Tau (τ) Scaling Law, not only will their compute specifications continue to double, but you can also expect to see huge improvements…”
UnifiedBus connects 4,096 NPUs inside the Atlas 960E
UnifiedBus is Huawei’s interconnect architecture for linking processors, memory, and other components within large AI computing systems.
Huawei applies UnifiedBus in the Atlas 960E, a 960 variant that ties up to 4,096 NPUs and gives them access to shared memory across the SuperPoD.
It combines UnifiedBus with Hi-ONE optical technology, extending high-speed optical connections deeper into the computing system.
The approach uses near-packaged optics, or NPOs, placing optical components closer to processors to improve transmission speeds and reduce energy consumption.
Huawei says this design helps the SuperPoD move data between thousands of processors without relying entirely on conventional optical connections outside the computing system.
The Atlas 960E can use approximately 5,500 Hi-ONE units instead of about 48,000 conventional 800G optical modules.
This configuration can reduce power consumption by more than 550 kilowatts across the processor interconnection system.
The architecture also gives the Atlas 960E 8 EFLOPS of FP8 computing performance while Huawei says it supports models containing up to 10 trillion parameters.
Atlas 960E systems can also connect into SuperClusters containing 512,000 NPUs, with the architecture ultimately supporting million-processor configurations.
The larger systems are important because Huawei cannot rely solely on individual accelerator performance to narrow the gap with Nvidia.
Its strategy combines more processors with faster communication, allowing thousands of chips to operate within a shared computing environment.
UnifiedBus therefore becomes important because thousands of processors must exchange data continuously during demanding AI training and inference workloads.
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